PIC18F8585T-I/PT【PDF 287/424 页】IC PIC MCU FLASH 24KX16 80TQFP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3881

283页 284页 285页 286页 [287页]288页 289页 290页 291页

2004 Microchip Technology Inc.

DS30491C-page 355

PIC18F6585/8585/6680/8680

24.2

Watchdog Timer (WDT)

The Watchdog Timer is a free-running, on-chip RC

oscillator which does not require any external compo-

nents. This RC oscillator is separate from the RC

oscillator of the OSC1/CLKI pin. That means that the

WDT will run even if the clock on the OSC1/CLKI and

OSC2/CLKO/RA6 pins of the device has been stopped,

for example, by execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device Reset (Watchdog Timer Reset). If the device is

in Sleep mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer wake-up). The TO bit in the RCON register

will be cleared upon a WDT time-out.

The Watchdog Timer is enabled/disabled by a device

configuration bit. If the WDT is enabled, software

execution may not disable this function. When the

WDTEN configuration bit is cleared, the SWDTEN bit

enables/disables the operation of the WDT.

The WDT time-out period values may be found in

Section 27.0

“Electrical

Characteristics”

under

parameter #31. Values for the WDT postscaler may be

assigned using the configuration bits.

24.2.1

CONTROL REGISTER

readable and writable register which contains a control

bit that allows software to override the WDT enable

configuration bit, only when the configuration bit has

disabled the WDT.

REGISTER 24-15: WDTCON REGISTER

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler if

assigned to the WDT and prevent it from

timing out and generating a device Reset

condition.

2: When a CLRWDT instruction is executed

and the postscaler is assigned to the

WDT, the postscaler count will be cleared

but the postscaler assignment is not

changed.

U-0

R/W-0

—

—SWDTEN

bit 7

bit 0

bit 7-1

Unimplemented: Read as ‘0’

bit 0

SWDTEN: Software Controlled Watchdog Timer Enable bit

= Watchdog Timer is on

= Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式